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	<title>PDTi &#187; ip reuse</title>
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	<description>Register management simplified</description>
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		<title>PDTi to Demonstrate SpectaReg Web Application for Simplifying Register Interfaces using IP-XACT 1.4 at DAC SPIRIT Meeting</title>
		<link>http://www.productive-eda.com/pdti-to-demonstrate-spectareg-web-application-for-simplifying-register-interfaces-using-ip-xact-1-4-at-dac-spirit-meeting/</link>
		<comments>http://www.productive-eda.com/pdti-to-demonstrate-spectareg-web-application-for-simplifying-register-interfaces-using-ip-xact-1-4-at-dac-spirit-meeting/#comments</comments>
		<pubDate>Tue, 13 May 2008 10:19:54 +0000</pubDate>
		<dc:creator>admin</dc:creator>
				<category><![CDATA[Web Release]]></category>
		<category><![CDATA[ip reuse]]></category>
		<category><![CDATA[IP-XACT]]></category>
		<category><![CDATA[register generation]]></category>
		<category><![CDATA[register-map]]></category>
		<category><![CDATA[SPIRIT Consortium]]></category>
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Collaborative register management and workflows are simplified by SpectaReg
SpectaReg provides a single source for all auto-generated deliverables including RTL, verification, software, and documentation

PDTi will demonstrate SpectaReg, a web application that enables chip developers to Simplify, Collaborate, Automate™ addressable register interfaces, during The SPIRIT Consortium’s general public meeting on Monday, June 9, at the Anaheim Convention [...]]]></description>
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		<title>Spec foul-ups fuel an EDA startup</title>
		<link>http://www.productive-eda.com/spec-foul-ups-fuel-an-eda-startup/</link>
		<comments>http://www.productive-eda.com/spec-foul-ups-fuel-an-eda-startup/#comments</comments>
		<pubDate>Mon, 26 Sep 2005 16:00:02 +0000</pubDate>
		<dc:creator>admin</dc:creator>
				<category><![CDATA[EETimes]]></category>
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		<category><![CDATA[esl tools]]></category>
		<category><![CDATA[ip reuse]]></category>
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After observing problems with managing specifications in chip-design environments, engineer-turned-entrepreneur Jeremy Ralph launched a company to provide electronic system-level (ESL) design tools that automatically generate code and documentation from specifications.

 http://www.eetimes.com/news/design/showArticle.jhtml?articleID=171200177


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		<title>Productivity Design Tools tackles chip-development productivity and IP reuse issues through ESL tools</title>
		<link>http://www.productive-eda.com/productivity-design-tools-tackles-chip-development-productivity-and-ip-reuse-issues-through-esl-tools/</link>
		<comments>http://www.productive-eda.com/productivity-design-tools-tackles-chip-development-productivity-and-ip-reuse-issues-through-esl-tools/#comments</comments>
		<pubDate>Sat, 24 Sep 2005 13:00:27 +0000</pubDate>
		<dc:creator>admin</dc:creator>
				<category><![CDATA[Press Releases]]></category>
		<category><![CDATA[esl tools]]></category>
		<category><![CDATA[ip reuse]]></category>
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		<description><![CDATA[* ESL software generates soft-IP from XML-based specifications
Vancouver BC, Canada &#8212; September 26, 2005 &#8212; Productivity Design Tools (PDTi), a new electronics design automation (EDA) company, today announced that it is developing electronic system level (ESL) software that manages specifications, enabling system-on-a-chip (SoC) developers to automate all aspects of code and documentation generation. PDTi provides [...]]]></description>
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