Posts Tagged ‘ip reuse’

PDTi to Demonstrate SpectaReg Web Application for Simplifying Register Interfaces using IP-XACT 1.4 at DAC SPIRIT Meeting

Tuesday, May 13th, 2008

  • Collaborative register management and workflows are simplified by SpectaReg
  • SpectaReg provides a single source for all auto-generated deliverables including RTL, verification, software, and documentation

PDTi will demonstrate SpectaReg, a web application that enables chip developers to Simplify, Collaborate, Automate™ addressable register interfaces, during The SPIRIT Consortium’s general public meeting on Monday, June 9, at the Anaheim Convention Center from 6:00pm to 9:00pm, at the 2008 Design Automation Conference (DAC).

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Spec foul-ups fuel an EDA startup

Monday, September 26th, 2005

After observing problems with managing specifications in chip-design environments, engineer-turned-entrepreneur Jeremy Ralph launched a company to provide electronic system-level (ESL) design tools that automatically generate code and documentation from specifications.

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Productivity Design Tools tackles chip-development productivity and IP reuse issues through ESL tools

Saturday, September 24th, 2005

* ESL software generates soft-IP from XML-based specifications

Vancouver BC, Canada — September 26, 2005 — Productivity Design Tools (PDTi), a new electronics design automation (EDA) company, today announced that it is developing electronic system level (ESL) software that manages specifications, enabling system-on-a-chip (SoC) developers to automate all aspects of code and documentation generation. PDTi provides chip developers with an extensible tool-based methodology that enables project-wide synchronization, automated re-engineering, and improved opportunities for reuse. The privately funded Company is focused on achieving efficiency improvements in chip development through better abstraction and reuse.

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