Verilog & VHDL Register RTL Generation
Your Verilog, VHDL or SystemVerilog register-map implementations contain register-files, memories, interrupts, masks, FIFOs, counters, plain old flip-flop and other memory-map elements. SpectaReg is flexible enough to handle them all while abstracting all but the most relevant information from the specification process.
Hand coding, connecting, and instantiating register-map elements isn’t much fun, nor is simulating and debugging them. Then once it’s done there’s always one bit-field or register that needs to be moved or resized, and the micro-architecture specification document needs to be updated and the programmers’ reference too. SpectaReg takes care of all of these headaches, so you can focus on creating interesting, value added logic.
The list of on-chip bus interfaces/protocols supported by SpectaReg.com is rapidly expanding for FPGA, ASIC, and ASSP SoC designs. Examples include ARM AMBA AHB and APB, IBM CoreConnect PLB and OPB, and Altera Avalon.