Hardware Verification
Generate verification code for simulating your design in e, Verilog, VHDL, SystemVerilog. Automatically insert assertions and coverage points.
Often more time is spent testing and debugging memory-mapped registers than you’d like. SpectaReg reduces the memory-map errors that are introduced so you can move on to testing other important features. Block-level and system level tests can be generated for register-map verification and validation. White-box artifacts like assertions, coverage-points, and diagnostics registers can all be automatically generated.
For hardware verification SpectaReg provides:
- register data structures, objects, methods, functions
- expected value modeling and verification
- per-bit-field coverage and cross-coverage automatically created
- register and protocol specific libraries
- OVM and VMM verification methodologies supported