PDTi

SpectaReg, from PDTi, is a collaborative register map automation tool for software/hardware interface design. SpectaReg’s web-browser GUI simplifies engineering workflows, cutting development time and costs. Specifications are easily captured into the tool and matching hardware logic, hardware verification, firmware, documentation and more are all rapidly auto-generated from a single source.

SpectaReg’s Streamlined Register Management Flow

• Develop & manage registers in a rich browser-based interface
• Align with IP-XACT XML as the single-source
• Auto-generate register code & docs from a central repository
  • VHDL, Verilog, SystemVerilog, C/C++, DITA, HTML, RALF, & more
• Grow & scale the methodology across projects, teams, components, locations & users
• Convert legacy register data into IP-XACT XML – SpectaReg has a data converter
• Support any register type & output – SpectaReg is extensible

SpectaReg Online or Onsite, your choice

Click on one of the options below for more information.

SpectaReg for the Whole Team

SpectaReg’s browser interface and code generation engine provides collaboration and synchronization across many important perspectives:

• RTL Register Development
• ESL Modeling, Integration & Optimization
• Embedded Firmware Development
• Verification Development
• Validation & Device Debug
• Engineering Management
• Technical Marketing, Applications & Support

RTL Register Developer

Manage register specs and auto-generate matching RTL register blocks. Ensure bit-for-bit consistency across the XML specification, and all derived outputs including synthesizable Verilog and VHDL RTL models. All types of registers and protocols are supported through SpectaReg’s extensible code generation engine, including ARM AMBA on-chip interconnect protocols. More info for RTL developers.

ESL Modeling

Utilize the auto-generated register abstractions in C/C++ and integrate with SystemC hooks for algorithm and architecture modeling, integration, and optimization of the system. Systematically achieve coherence between the ESL model, Software and RTL developers with the SpectaReg register management methodology.

Embedded Firmware Developer

Auto generate C/C++ firmware for accessing registers using your preferred technique, including: macros, structures, classes, interrupts, and more. More info for firmware developers.

Verification Developer

Abstract registers in your preferred verification methodology and language including SystemVerilog random constrained methodologies under VMM and OVM. Employ auto-generated tests and register-smart components for the verification environment. Utilize generated code and libraries for register access, expected value modeling, test coverage, and cross coverage. More info for verification developers.

Validation & Silicon Debug

Use auto-generated C to test register hardware and software in the lab. Auto-generate code and docs for managing relationships between registers and test case coverage. Track down bugs with diagnostic and debug registers.

Technical Publications

Keep register-map documentation error-free and synchronized with the most up-to-date design. SpectaReg makes single-source a reality for your documentation. More info about SpectaReg for register documentation.

Engineering Manager

Track real-time project register statistics and manage user access to the register descriptions. Assure a consistent, correct by construction methodology. Keep the team focused on core activities without having to manage homegrown tool development.

Technical Marketing, Applications & Support

Learn which registers are the most popular with the customer. SpectaReg helps optimize externally facing registers to ensure you and the customer have all the information you need. More info on SpectaReg for marketing & applications.