Hierarchical register-map specs are easily captured into SpectaReg as you decompose the system, define features, develop algorithms, and partition hardware / software -- it’s easier than using an XML-editor, word-processor or spreadsheet. Low-level implementation details are abstracted and you are not required to learn a new language.

Chances are that you are using memory mapped registers as a configuration and status interface between your embedded software and FPGA logic. FPGA register-maps can be a pain to maintain in Verilog, VHDL, C/C++ and documentation views. SpectaReg automates this allowing you to maintain registers at the electronics system level (ESL).

Register maps are so intrinsic and widespread that a considerable proportion of valuable engineering hours go into specifying, implementing and debugging the various register views. SpectaReg is easy to use, easy to adopt and provides maximum productivity.

SpectaReg comes with an embedded software API for reading, writing and testing registers and bit-fields from C - the PDTi Hardware Abstraction Layer in C HALiC.

SpectaReg generates a variety of useful register-map outputs for embedded software development, these include...

Keeping the register-map documentation error-free and synchronized with the design, can be a real pain, especially when things are constantly changing. SpectaReg makes this easy by automatically generating register-map documentation from the specification; and the documentation is generated at the same time as the RTL so you’re always in sync with the design.

Often more time is spent testing and debugging memory-mapped registers than you'd like. SpectaReg reduces the memory-map errors that are introduced so you can move on to testing other important features. Block-level, white-box and system level tests can be generated ...

Your Verilog, VHDL or SystemVerilog register-map implementations contain register-files, memories, interrupts, masks, FIFOs, counters, plain old flip-flop and other memory-map elements. SpectaReg is flexible enough to handle them all while abstracting all but the most relevant information from the specification process.