SpectaReg generates code and documentation from the SOM by resolving open-source templates to produce your desired outputs. The Python-based templates can be modified to suit your coding style and variable naming conventions. The example component ships with open-source templates for VHDL RTL, Verilog RTL, VHDL test-bench, C, C++, HTML, and DocBook XML. In addition, PDTi supports SystemVerilog, Specman e, DITA XML, and Frame (XML / SGML). Additional generators can be created for most any output format, and you can differentiate your outputs with customized templates.