SpectaReg represents memory-maps in terms of an open-source Python Specification Object Model, derived from IP-XACT but extended to include new classes of memory-map objects, and further extensible to include your custom classes (with your custom attributes and relationships). You can define specific types of RAMs, register-files, counters, interrupts, FIFOs and other memory-map elements – these become available during specification time. You can define cross-reference relationships between classes, enabling indirectly accessed registers, paged RAM windows, complex interrupt trees with status and masking.