Chances are that you are using memory mapped registers as a configuration and status interface between your embedded software and FPGA logic. FPGA register-maps can be a pain to maintain in Verilog, VHDL, C/C++ and documentation views. SpectaReg automates this allowing you to maintain registers at the electronics system level (ESL).

PDTi’s template-based generation system is flexible enough to support any FPGA platform. In particular we are working to support templates for the following standard FPGA SoC platforms:

Outputs, including verification and validation tests are generated at the click of a mouse. Once your register maps are captured into SpectaReg it’s easier to port your designs to different FPGAs, processors, and interconnect busses by simply changing the generation templates.