The name SpectaReg is derived from specification-to-generation. Register-map specifications provide a contract between stakeholders from which interdisciplinary register views are generated. This single source approach eliminates register-map inconsistencies...

Capturing register-map intent into SpectaReg through the UI is easy -- no new language is required and implementation details are abstracted. The graphical environment facilitates collaboration and provides interactive validation.

SpectaReg stores your register-map specifications in an extended version of the SPIRIT Consortium’s IP-XACT XML format (IEEE P1685). This is both a human and machine readable format which can be edited manually using an XML editor and versioned in your source control system.

SpectaReg represents memory-maps in terms of an open-source Python Specification Object Model, derived from IP-XACT but extended to include new classes of memory-map objects, and further extensible to include your custom classes (with your custom attributes and relationships). You can define specific types of RAMs, register-files, counters, interrupts, FIFOs and other memory-map elements – these become available during specification time.

SpectaReg ships with an open source reference example, illustrating how configuration, interrupt, and status registers are specified for hierarchical and channelized / time-sliced components.