SpectaReg ships with an open source reference example, illustrating how configuration, interrupt, and status registers are specified for hierarchical and channelized / time-sliced components. Open extensions to SpectaReg’s Specification Object Model show how typing and cross-referencing between various classes of memory-map elements can model your most complex memory map requirements. With the click of a mouse thousands of lines of code are generated as SpectaReg resolves open-source templates for VHDL RTL, Verilog RTL, VHDL test-bench, C, C++, HTML, DocBook XML, and other formats.