The register-map pattern is widespread in ASSP, ASIC, SoC and FPGA design. This article is based on an FPGA-based embedded system using Altera’s SOPC Builder and NIOS II soft-processor. The concepts described in the article also apply to an ASIC flow and to FPGA systems that use other embedded processors. To illustrate these concepts the article describes a slave component – a simple programmable traffic light controller (TLC).
How to simplify the process of specifying register-maps and auto-generating code and other deliverables.
March 28th, 2007
Spec foul-ups fuel an EDA startup
September 26th, 2005
After observing problems with managing specifications in chip-design environments, engineer-turned-entrepreneur Jeremy Ralph launched a company to provide electronic system-level (ESL) design tools that automatically generate code and documentation from specifications.
Productivity Design Tools tackles chip-development productivity and IP reuse issues through ESL tools
September 24th, 2005
* ESL software generates soft-IP from XML-based specifications
Vancouver BC, Canada — September 26, 2005 — Productivity Design Tools (PDTi), a new electronics design automation (EDA) company, today announced that it is developing electronic system level (ESL) software that manages specifications, enabling system-on-a-chip (SoC) developers to automate all aspects of code and documentation generation. PDTi provides chip developers with an extensible tool-based methodology that enables project-wide synchronization, automated re-engineering, and improved opportunities for reuse. The privately funded Company is focused on achieving efficiency improvements in chip development through better abstraction and reuse.