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Corporate
Standards & Programs
Altera
Altera (Nasdaq: ALTR) is a world leader in providing programmable solutions that enable system and semiconductor companies to rapidly and cost-effectively innovate, differentiate and win in their markets. PDTi is a member of the Altera® Commitment to Cooperative Engineering Solutions (ACCESS) program, which ensures that Altera customers have a solid design methodology to develop their FPGA and HardCopy® ASIC designs. Find out more about Altera’s FPGA, CPLD and ASIC devices at www.altera.com.
ARM
ARM designs the technology that lies at the heart of advanced digital products, from wireless, networking and consumer entertainment solutions to imaging, automotive, security and storage devices. ARM’s comprehensive product offering includes 32-bit RISC microprocessors, graphics processors, video engines, enabling software, cell libraries, embedded memories, high-speed connectivity products, peripherals and development tools. Combined with comprehensive design services, training, support and maintenance, and the company’s broad Partner community, they provide a total system solution that offers a fast, reliable path to market for leading electronics companies.
Mentor Graphics
Mentor Graphics Corporation (Nasdaq: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronics and semiconductor companies.
PDTi participates in the Questa Vanguard Program (QVP) which Mentor has established to bring customers world-class product integrations and interoperability to enhance their Questa verification options and build a strong and comprehensive SystemVerilog ecosystem.
Synopsys
Synopsys, Inc. (Nasdaq: SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys’ comprehensive, integrated portfolio of implementation, verification, IP manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has more than 65 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com.
PDTi participates in the Synopsys VMM and System Level Catalyst Programs.
Xilinx
Xilinx (Nasdaq: XLNX) is a worldwide leader of programmable logic solutions. PDTi participates in the Xilinx Alliance Program (XAP). This program assures the best available “total solutions” combining Xilinx programmable logic with key technologies from XAP members, including IP cores, EDA, DSP and embedded development tools, design services, board-level products, integrated circuits, and electronic components.
IP-XACT (IEEE P1685)
Since 2004 PDTi has been a reviewing member of the SPIRIT Consortium, a global organization focused on establishing multi-faceted IP/tool integration standards that drive sustainable growth in electronic design. IP-XACT, The Consortium’s official set of specifications for IP meta-data and tool interfaces, has been released to the public and is currently in review with the IEEE P1685 Working Group. The Consortium is comprised of leading EDA, IP, system integration, and semiconductor companies dedicated to the adoption of a unified set of specifications for configuring, integrating, and verifying IP in advanced SoC design tool sets. In 2009 the SPIRIT Consortium merged with Accellera, the leading standards organization developing language based standards used by system, semiconductor, IP and EDA companies.
OCP-IP
OCP International Partnership (OCP-IP) is a non-profit semiconductor industry consortium formed to administer the support, promotion and enhancement of the Open Core Protocol (OCP) specification. OCP is the only fully supported, openly licensed, complete interface socket for intellectual property (IP) cores. OCP addresses design, verification and testing issues common to IP core reuse in “plug-and-play” system-on-chip (SOC) products. Additional information is available at www.ocpip.org.
OVM
PDTi supports the open source Open Verification Methodology (OVM) and is an OVM partner. The OVM is the result of joint development between Cadence and Mentor Graphics to facilitate true SystemVerilog interoperability with a standard library and a proven methodology.
System Level Catalyst
PDTi participates in Synopsy’s System Level Catalyst Program, which promotes interoperability between system-level design solutions. PDTi’s participation in this program provides further integration and validation between SpectaReg, the industry’s leading register management and collaboration tool and a number of Synposys products including Innovator, Confirma and DesignWare.
SystemVerilog
IEEE 1800 SystemVerilog is the industry’s first unified hardware description and verification language (HDVL) standard. SystemVerilog is a major extension of the established IEEE 1364 Verilog language. It was developed originally by Accellera to dramatically improve productivity in the design of large gate-count, IP-based, bus-intensive chips. SystemVerilog is targeted primarily at the chip implementation and verification flow, with powerful links to the system-level design flow. SystemVerilog has been adopted by 100’s of semiconductor design companies and is supported by more than 75 EDA, IP and training solutions worldwide.
VMM
PDTi participates in Synopsy’s VMM Catalyst Program, which promotes the development and use of EDA tools, verification IP, training, and services which support the VMM verification methodology. PDTi SpectaReg is VMM enabled, supporting code generation of the VMM Register Abstraction Layer File (RALF) for use with the VMM Register Abstraction Layer (RAL) tool.