Archive for the ‘In the Media’ Category

Challenges in Cloud Computing for EDA

Tuesday, October 26th, 2010

By Jeremy Ralph, CEO PDTi

The top level benefits of cloud computing – including economic, flexibility, and simplification benefits are well known and widely experienced across various industries. Software-as-a-Service (SaaS) is a great example of how one level of cloud computing has created significant industry transformation, and now represents over 25% of revenue in some software markets. EDA is slowly joining this transformation, with challenges remaining for both vendors and customers. For customers, the most commonly listed issues with cloud computing seem to be security and design flow limitations. The former is a topic to itself, while design flow limitations are of course more specific to EDA. This then becomes the vendor challenge, taking a new technology and applying it to EDA to solve problems in better ways and by taking advantage of key cloud computing attributes, not necessarily by simply moving existing applications onto some type of cloud service. Read the full article at Chip Design Magazine.

How to simplify the process of specifying register-maps and auto-generating code and other deliverables.

Wednesday, March 28th, 2007

The register-map pattern is widespread in ASSP, ASIC, SoC and FPGA design. This article is based on an FPGA-based embedded system using Altera’s SOPC Builder and NIOS II soft-processor. The concepts described in the article also apply to an ASIC flow and to FPGA systems that use other embedded processors. To illustrate these concepts the article describes a slave component – a simple programmable traffic light controller (TLC).

Spec foul-ups fuel an EDA startup

Monday, September 26th, 2005

After observing problems with managing specifications in chip-design environments, engineer-turned-entrepreneur Jeremy Ralph launched a company to provide electronic system-level (ESL) design tools that automatically generate code and documentation from specifications.


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