The register-map pattern is widespread in ASSP, ASIC, SoC and FPGA design. This article is based on an FPGA-based embedded system using Altera’s SOPC Builder and NIOS II soft-processor. The concepts described in the article also apply to an ASIC flow and to FPGA systems that use other embedded processors. To illustrate these concepts the article describes a slave component – a simple programmable traffic light controller (TLC).
How to simplify the process of specifying register-maps and auto-generating code and other deliverables.
Wednesday, March 28th, 2007
Spec foul-ups fuel an EDA startup
Monday, September 26th, 2005
After observing problems with managing specifications in chip-design environments, engineer-turned-entrepreneur Jeremy Ralph launched a company to provide electronic system-level (ESL) design tools that automatically generate code and documentation from specifications.