PDTi™

For FPGA and SoC development teams, PDTi products dramatically simplify the process of collaboratively converting high-level specifications into implementation deliverables.

Our approach is

• Customer focused
• Standards based
• Easy to learn and use
• Flexible / extensible
• Cost effective

SpectaReg makes memory-mapped registers really easy for chip development teams. Specify register-maps in a rich and intuitive UI then generate dependent code and documentation with the click of a mouse.

You provide the memory-map register specifications; PDTi provides verified and documented RTL and embedded software based on your specs. Special discounts for register-maps targeting standard platforms like ARM® AMBA™, Altera® NIOS® II with Avalon®, and Xilinx® PowerPC™ / MicroBlaze™ with CoreConnect™.

Keep your embedded software’s hardware abstraction layer in-sync with the changing RTL design. Automatically generate embedded software for easily interfacing with memory-mapped registers.

Automatically generate your Verilog, VHDL, and/or SystemVerilog register-map RTL code. Make it easy to modify your address-map and keep the rest of the team in-sync. SpectaReg is flexible to support all your register and bit-field types.

Generate verification code for simulating your design in e, Verilog, VHDL, SystemVerilog. Automatically insert assertions and coverage points. Generate C/C++ tests and TLM SystemC for modelling. Simplify the creation of diagnostics and debugging registers.

SpectaReg is a register-map content management system. Generate your register-map documentation in DITA, DocBook, SGML, HTML, Frame, Word or whatever format you prefer.